1. Field of the Invention
The present invention relates to a D/A converter (DAC) for converting a digital signal to an analog signal by switching on/off a plurality of current sources based on the digital signal.
2. Description of the Background Art
At the present time, an oversampling .DELTA..SIGMA. conversion technique is widely used as the voice grade data conversion technique. FIG. 30 is a block diagram of an A/D converter using the oversampling .DELTA..SIGMA. conversion technique. As shown in FIG. 30, an analog input signal AI is applied to an anti-aliasing filter 11. The anti-aliasing filter 11 removes the high-frequency components of the analog input signal AI to apply the resultant analog input signal AI to a .DELTA..SIGMA. modulator 12.
The .DELTA..SIGMA. modulator 12 noise-shapes the analog input signal AI while oversampling the analog input signal AI at a frequency (n (.gtoreq.2).multidot.fS) higher than a sampling frequency fS to apply a .DELTA..SIGMA. modulated digital signal to a decimation filter 13. The decimation filter 13 extracts digital signals at a rate of one in every n digital signals from the .DELTA..SIGMA. modulator 12 to output each of the extracted digital signals as a digital output signal DO.
The .DELTA..SIGMA. modulator 12 comprises a subtracter 14, an integrator 15, a quantizer 16, and an internal DAC 17. The integrator 15 integrates an analog difference signal outputted from the subtracter 14. The quantizer 16 quantizes the output from the integrator 15 to output a digital signal (containing noise components) to the decimation filter 13 and to the internal DAC 17. The internal DAC 17 converts the digital signal to an analog signal to feed back the analog signal for subtraction to the subtracter 14. The integrator 15 functions to integrate the analog difference signal for a period of time 1/(n.multidot.fS) to cause a delay of one oversampling time.
The subtracter 14 then subtracts the analog signal for subtraction (corresponding to the analog signal AI delayed by one oversampling time) provided from the internal DAC 17 from the analog input signal AI provided from the anti-aliasing filter 11 to output the analog difference signal to the integrator 15. As a result, a noise shaping group formed by the subtracter 14, the integrator 15, the quantizer 16, and the internal DAC 17 removes the noise components of the analog input signal AI to apply a high-accuracy digital signal to the decimation filter 13.
FIG. 31 is a block diagram of a D/A converter using the oversampling .DELTA..SIGMA. conversion technique. As shown in FIG. 31, an interpolation filter 21 performs an operation based on original data given from a digital input signal DI to determine interpolation data, and then interpolates the interpolation data into the original data to output a digital signal oversampled at a frequency n .multidot.fS to a .DELTA..SIGMA. modulator 22.
The .DELTA..SIGMA. modulator 22 noise-shapes the oversampled digital signal to apply the noise-shaped digital signal to an internal DAC 23. The internal DAC 23 converts the .DELTA..SIGMA. modulated digital signal from the .DELTA..SIGMA. modulator 22 to an analog signal to output the analog signal to a low-pass filter 24. The low-pass filter 24 removes the high-frequency components of the analog signal provided from the internal DAC 23 to output an analog output signal AO.
The .DELTA..SIGMA. modulator 22 comprises a subtracter 25, an integrator 26, and a quantizer 27. The integrator 26 integrates a digital difference signal outputted from the subtracter 25. The quantizer 27 quantizes the output from the integrator 26 to output a .DELTA..SIGMA. modulated digital signal (containing noise components) to the internal DAC 23 and to feed back the .DELTA..SIGMA. modulated digital signal as a digital signal for subtraction to the subtracter 24. The integrator 26 functions to integrate the digital difference signal for a period of time 1/(n.multidot.fS) to cause a delay of one oversampling time.
The subtracter 25 then subtracts the digital signal for subtraction (corresponding to the digital signal from the interpolation filter 21 which is delayed by one oversampling time) provided from quantizer 27 from the digital signal provided from the interpolation filter 21 to output the digital difference signal to the integrator 26. As a result, a noise shaping group formed by the subtracter 25, the integrator 26, and the quantizer 27 removes the noise components of the digital signal to apply a high-accuracy digital signal to the internal DAC 23.
As above described, the oversampling .DELTA..SIGMA. conversion technique requires the internal DAC in each of the A/D and D/A converters. The internal DAC in the AID converter serves as a feedback signal processing circuit of the noise shaping group, and the internal DAC in the D/A converter serves as a circuit for converting the noise-shaped digital signal to the analog signal. The conventional internal DACs have been 1-bit DACs. The use of the 1-bit DAC provides a simple structure and ensures the linearity of an analog output from the DAC relative to a digital input to the DAC. On the other hand, the 1-bit DAC is disadvantageous in producing a large amount of quantization noise and having the problem of system stability. To overcome the disadvantages, multi-bit DACs have recently been introduced as the internal DACs. However, the multi-bit DAC presents difficulties in matching between the elements thereof, and fails to provide the linearity which has been ensured by the 1-bit DAC.
FIG. 32 illustrates an internal structure of a conventional 3-bit D/A converter. As shown in FIG. 32, unit current sources IS1 to IS7 are connected at their first ends to a power supply Vcc, and connected at their second ends to the first ends of switches S1 to S7, respectively. The second ends of the switches S1 to S7 are commonly connected to a node N1 serving as an output portion. The 3-bit D/A converter requires (2.sup.3 -1) current sources as shown in FIG. 32. The current sources IS1 to IS7 supply currents I1 to I7 having the same quantity IE.
A switch control circuit 10 outputs a control signal SC to the switches S1 to S7 on the basis of a digital signal DIG to turn on some of the switches S1 to S7 which are arranged in ascending order of reference characters starting with the switch S1 while turning off the remaining switches, the number of switches turned on being dependent upon the digital signal DIG.
For example, if the digital signal DIG is "011" (3), the switch control circuit 10 outputs the control signal SC which turns on the switches S1 to S3 and turns off the switches S4 to S7, as shown in FIG. 33. If the digital signal DIG is "010" (2), the switch control circuit 10 outputs the control signal SC which turns on the switches S1 and S2 and turns off the switches S3 to S7, as shown in FIG. 34.
Current at the node N1 is provided as an output current lout to an I-V converter 2. The I-V converter 2 current-to-voltage converts the output current Iout to an output voltage Vout which is an analog signal. The output current Iout equals 3.multidot.IE in the arrangement shown in FIGS. 33, and the output current lout equals 2.multidot.IE in the arrangement shown in FIG. 34.
In this manner, the multi-bit D/A converter employing current sources enables a predetermined number of current sources depending on the input digital data (DIG) to convert the digital data DIG to the analog signal (output voltage Vout).
Japanese Patent Application Laid-Open No. 4-152715 (1992) discloses a D/A converter which randomly selects a given number of capacitors depending on an input code to perform D/A conversion.
However, perfect coincidence of the characteristics of the unit current sources IS1 to IS7 (the quantities of currents I1 to I7) is difficult because of variations in process and the influences of peripheral circuit elements during layout.
The conventional 3-bit D/A converter enables current sources in response to the digital input signal (DIG), starting with the same current source at all times.
For example, if the digital signal DIG is not "000", the switch S1 is always turned on to enable the current source IS1.
This causes a particular current source (the current source IS1 in the arrangement shown in FIG. 32) to be enabled an inordinate number of times Thus, the difference in characteristics between the individual current sources pronouncedly appears in the output from the D/A converter, resulting in the degradation of the linearity.
The conventional multi-bit D/A converter constructed as above described has been disadvantageous in poor linearity of the analog output relative to the digital input.